An FPGA-based Point Pattern Matching Processor with Application to Fingerprint Matching - Computer Architectures for Machine Perception, 1995. Proceedings. CAMP '95

W e describe the design and synthes is of a highper formance coprocessor f o r po in t pa t t e rn matching wi th application t o f ingerpr in t matching using Splash 2 a n attached processor for SUN S P A R C s t a t i o n hosts. E a c h of t h e field programmable gate array ( F P G A ) based processing e lements (PES) i s programmed using VHDL behavioral modeling. Using the s imula t ion tools, t he program logic i s verified. T h e f inal control bit s t ream for the PES is generated using the synthesis tools. T h e po in t feature matching coprocessor can run at a peak speed of 17.1 M H z per feature vector of a f in gerprint. With 65 f ea tures per f ingerprint, t he ma tch ing speed has been projected a t the rate of 2.6 * lo5 f in gerprints/sec. T h e synthesized coprocessor was tested o n a 10,000 f ingerpr in t database.